Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor typically includes two conductive electrodes separated by a dielectric layer. The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage. Data is stored in the memory cells during a write mode and retrieved from the memory cells during a read mode. The data is transmitted on signal lines, sometimes referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. However, each such memory cell is coupled to, or associated with, only one digit line of a digit line pair through an access transistor.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access transistors for a given word line address, the charge of the selected memory cells, i.e. the charge stored in the associated capacitor, are shared with their associated digit lines, and data is sensed and latched to the digit line pairs.
As DRAMs increase in memory cell density by decreasing memory cell area, there is an ongoing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell area and its accompanying capacitor area, since capacitance is generally a function of electrode area. Additionally, there is a continuing goal to further decrease memory cell area.
A principal method of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom electrode of the capacitor. Such container structures may have shapes differing from a substantially cylindrical form, such as an oval or other three-dimensional container. The container structures may further incorporate fins.
Another method of increasing cell capacitance is through the use of high dielectric constant material in the dielectric layer of the capacitor. In order to achieve the charge storage efficiency generally needed in 256 megabit(Mb) memories and above, materials having a high dielectric constant, and typically dielectric constants greater than 20, can be used in the dielectric layer between the bottom electrode and the top electrode of the capacitor. The dielectric constant is a characteristic value of a material and is generally defined as the ratio of the amount of charge that can be stored in the material when it is interposed between two electrodes relative to the charge that can be stored when the two electrodes are separated by a vacuum.
Unfortunately, high dielectric constant materials are often incompatible with existing processes. One cause of such incompatibility can be adverse chemical reactions or oxygen diffusion between the material of the dielectric layer and the material of an adjoining electrode due to direct contact.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative capacitor structures and methods for producing same.